The invention generally relates to a method used to increase the density of devices formed on a semiconductor wafer. More particularly, the invention relates to a method used to reduce the dimensions of devices formed on a semiconductor wafer.
Devices made from semiconductor materials are used to create memory circuits in electrical components and systems. Memory circuits are the backbone of such devices as data and instruction sets are stored therein. Minimizing the amount of natural resources and space consumed by memory circuits is a primary motivation in the designing of such circuits. As the design of memory circuits has moved from two-dimensional designs to three-dimensional designs, more emphasis is being made to minimize the space required to build structures, while maintain the integrity and strength of same, which becomes more important as more elements are incorporated into a space, the greater the cost in having to replace that component should one element therein fail.
Electrical connections between dielectric layers and electrical components of an integrated circuit are required to be strong. Likewise, the electrical components themselves must be strong enough to endure harsh environmental conditions during continued manufacturing processes and a subsequent use life. Therefore, the connections between the electrical components and the wafer must be strong.
As the dimensions for structures formed on a semiconductor wafer diminish, tools currently available to create these devices reach their limits. By way of example, for a 32 nanometer patterning of a pillar structure, the currently available 193 nanometer immersion tools will fail to create such small devices. To use such tools, the use of which is desired to minimize the cost of tooling to fabricate the new smaller devices, additional steps are required to be introduced into the manufacturing process. One such process is double exposure/double patterning techniques.
It has been proposed to use negative resist to perform double exposure on line/space structures. Similar concepts have been applied to pillar structures by using contact mask structures to print pillar structures using a negative resist. The resolution capability of the 193 nanometer immersion tools with a negative resist lacks predictability and reliability.